The present invention relates to the field of instruction-controlled digital computers and specifically to methods and apparatus associated with the channels within data processing systems.
In prior art, channels have been architecturally defined as that part of the data processing system which serves control units associated with the system's input/output (I/O) devices. Channels have been independent and discrete apparatus having their own set of commands which enable the I/O devices to read and write data while the remainder of the system concurrently processes instructions not necessarily related to I/O devices. Each channel has had its own instructions in system storage which have been fetched and processes under supervisory program control.
Channels are generally of three types, selector, byte multiplexor, and block multiplexor. Selector channels and block multiplexor channels are generally associated with high-speed devices, while byte multiplexor channels are usually associated with low-speed devices. A plurality of I/O devices are connected to a channel through a control unit. Byte multiplexor channels and block multiplexor channels allow interleaved transfer of data from multiple devices attached to the same physical channel interface.
While channels function somewhat independently of instructions executed by the data processing system, the data processing system maintains supervisory control over the channel and I/O operations. Channels are therefore processors of information which have some independence from other system processors (e.g., I-unit) and hence increase the concurrency of the processing of information by the system.
Whereas I/O devices operate at comparatively limited speeds which limit the maximum data rate over a channel, frequently due to mechanical limitations, and whereas electronic circuits operate at much higher speeds, it is desirable that high-speed circuits be shared by a plurality of slow-speed I/O devices in order to make more efficient use of high-speed circuit capabilities. In prior art channel structures in which channel apparatus has been dedicated on a per channel basis, the circuits in one channel have not been readily shared with other channels.
In channel structures with shared high-speed apparatus, it is desirable that control operations, such as recording the number of bytes transferred, be carried out without unduly degrading system performance. There is a need for improved methods and apparatus for processing control information in channel apparatus.